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| toshiba toshiba corporation 1/86 tlcs-90 series tmp90c802a/803a the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers tmp90c802ap/tmp90c802am TMP90C803Ap/TMP90C803Am 1. outline and characteristics the tmp90c802a is a high-speed advanced 8-bit microcontroller applicable to a variety of equipment. with its 8-bit cpu, rom, ram, timer/event counter and gen- eral-purpose serial interface integrated into a single cmos chip, the tmp90c802a allows the expansion of external memories (up to 56k byte). the TMP90C803A is the same as the tmp90c802a but without the rom the tmp90c802ap/803ap is in a dip product. the tmp90c802am/8803am is in a sop (small outline package). the characteristics of the tmp90c802a include: (1) powerful instructions: 163 basic instructions, including multiplication, division, 16-bit arithmetic operations, bit manipulation instructions (2) minimum instruction executing time: 320ns (at 12.5mhz oscillation frequency) (3) internal rom: 8k byte (the TMP90C803A does not have a built-in rom.) (4) internal ram: 256 byte (5) memory expansion external memory: 56k byte (6) general-purpose serial interface (1 channel) asynchronous mode, i/o interface mode (7) 8-bit timers (4 channels): (1 external clock input) (8) port with zero cross detection circuit (1 input) (9) input/output ports (tmp90c802a: 32 pins, 90c803a: 6 pins) (10) interrupt function: 8 internal interrupts and 3 external interrupts (11) micro direct memory access (dma) function (4 channels) (12) watchdog timer (13) standby function (4 halt modes)
2/86 toshiba corporation tmp90c802a/803a figure 1. tmp90c802a block diagram toshiba corporation 3/86 tmp90c802a/803a 2. pin assignment and functions the assignment of input/output pins, their names and functions are described below. 2.1 pin assignment figure 2.1 shows pin assignment of the tmp90c802a/803a. figure 2.1. pin assignment 4/86 toshiba corporation tmp90c802a/803a 2.2 pin names and functions the names of input/output pins and their functions are summarized in table 2.2. table 2.2 pin names and functions (1/2) pin name no. of pins i/o 3 states function p00 ~ p07 /d0 ~ d7 8 i/o port 0: 8-bit i/o port that allows selection of input/output on byte basis 3 states data bus: also functions as 8-bit bidirectional data bus for external memory p10 ~p17 /a0 ~ a7 8 i/o port 1: 8-bit i/o port that allows selection on byte basis output address bus: the lower 8 bits address bus for external memory p20 ~ p27 /a8 ~ a15 8 i/o port 2: 8-bit i/o port that allows selection on bit basis output address bus: the upper 8 bits address bus for external memory p31 /rxd 1 input port 31: 1-bit input port receives serial data p32 /sclk 1 output port 32: 1-bit output port serial clock output p33 /txd 1 output port 33: 1-bit output port transmitter serial data p35 /rd 1 output port 35: 1-bit output port read: generates strobe signal for reading external memory p36 /wr 1 output port 36: 1-bit output port write: generates strobe signal for writing into external memory p37 /w ait /to1 1 input port 37: 1-bit input port wait: input pin for connecting slow speed memory or peripheral lsi output timer output 1: output of timer 0 or 1 p80 /into 1 input port 80: 1-bit input port interrupt request pin 0: interrupt request pin (level/rising edge is programmable) p81 /int1 /ti2 1 input port 81: 1-bit input port interrupt request pin 1: interrupt request pin (rising edge) timer input 2: counter/capture trigger signal for timer 2 nmi 1 input non-maskable interrupt request pin: falling edge interrupt request pin clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up internally during resetting. ea 1 input external access: connects with v cc pin in the tmp90c802a using internal rom, and with gnd pin the TMP90C803A with no internal rom. reset 1 input reset: initializes the tmp90c802a/803a. (built-in pull-up resister) x1/x2 2 input/output pin for quartz crystal or ceramic resonator (1 ~ 12.5mhz) v cc 1 power supply (+5v) v ss (gnd) 1 ground (0v) toshiba corporation 5/86 tmp90c802a/803a 3. operation this chapter describes the functions and the basic operations of the tmp90c802a in every block. 3.1 cpu tmp90c802a includes a high performance 8-bit cpu. for the function of the cpu, see the book tlcs series cpu core architecture concerning cpu operation. this chapter explains exclusively the functions of the cpu of tmp90c802a which are not described in that book. 3.1.1 reset the basic timing of the reset operation is indicated in figure 3.1. in order to reset the tmp90c802a, the reset input must be maintained at the ??level for at least ten system clock cycles (10 stated: 2 m sec at 10mhz) within an operating voltage band and with a stable oscillation. when a reset request is accepted, all i/o ports (port 0/data bus d0 ~ d7, port 1/ address bus a0 to a7, port 2/address bus a8 to a15) function as input ports (high impedance state). output ports (p32, p33, p35 (rd ) and p36 (wr ) and clk turn to ?? input ports remain unchanged. the registers of the cpu also remain unchanged. note, however, that the program counter ?c?and the interrupt enable ?g iff are cleared to ?? register a shows an unde?ed status. when the reset is cleared, the cpu starts executing instructions from the address 0000h. figure 3.1. reset timing 3.1.2 exf (exchange flag) for tmp90c802a, ?xf? which is inverted when the com- mand ?xx?is executed to transfer data between the main register and the auxiliary register, is allocated to the ?st bit of memory address ffd2h. 6/86 toshiba corporation tmp90c802a/803a 3.1.3 wait control for tmp90c802a, a wait control register (waitc) is allocated to the 6th and 7th bits of memory address ffc7h. 3.2 memory map the tmp90c802a supports a program memory of up to 64k bytes. the program/data memory may be assigned to the address space from 0000h to ffffh. (1) internal rom the tmp90c802a internally contains an 8k byte rom. the address space from 0000h ~ 1fffh is provided to the rom. the cpu starts executing a program from 0000h by resetting. the addresses 0010h ~ 007fh in this internal rom area are used for the entry area for the interrupt processing. the TMP90C803A does not have a built-in rom; therefore, the address space 0000h ~ 1ffffh is used as external memory space. (2) internal ram the tmp90c802a also contains a 256 byte ram, which is allocated to the address space from ffc0h ~ ffbfh. the cpu allows the access to the whole ram area (ff00h ~ ffbfh, 192 bytes) by a short operation code (opcode) in a ?irect addressing mode? the addresses from ff30h ~ ff7fh in this ram area can be used as parameter area for micro dma processing (and for any other purposes when the micro dma function is not used). (3) internal i/o the tmp90c802a provides a 48-byte address space as an internal i/o area, whose addresses range from ffc0h ~ ffefh. this i/o area can be accessed by the cpu using a short opcode in the ?irect address ing mode? figure 3.2 is a memory map indicating the area accessible by the cpu in the respective addressing mode. toshiba corporation 7/86 tmp90c802a/803a figure 3.2. memory map 3.3 interrupt functions the tmp90c802a supports a general purpose interrupt process- ing mode and a micro dma processing mode that enables automatic data transfer by the cpu for internal and external interrupt requests. after the reset state is released, all interrupt r equests are processed in the general purpose interrupt processing mode. however, they can be processed in the micro dma processing mode by using a mda enable register to be described later. figure 3.3 (1) is a ?w chart of the interrupt response sequence. 8/86 toshiba corporation tmp90c802a/803a figure 3.3 (1). interrupt response flowchart when an interrupt is requested, the source of the interrupt transmits the request to the cpu via an internal interrupt controller. the cpu starts the interrupt processing if it is a non-maskable or maskable interrupt requested in the ei state. however, a maskable interrupt requested in the di state (iff = ?? is ignored. having acknowledged an interrupt, the ?pu?reads out the interrupt vector from the internal interrupt controller to ?d out the interrupt source. then, the cpu checks if the interrupt requests the general purpose interrupt processing or the micro dma processing, and proceeds to each processing. as the reading of an interrupt vectors is performed in the internal operating cycles, the bus cycle results in dummy cycles. 3.3.1 general purpose interrupt processing a general purpose interrupt is processed as shown in figure 3.3 (2). the cpu stores the contents of the program counter pc and the register pair af (including the interrupt enable ?g (iff) before the interrupt) into the stack, and resets the interrupt enable ?g iff to ??(disable interrupts). in then transfers the value of the interrupt vector ??to the program counter, and the processing jumps to an interrupt processing program. the overhead for the entire process from accepting an interrupt to jumping to an interrupt processing program is 20 states. toshiba corporation 9/86 tmp90c802a/803a figure 3.3 (2). general purpose interrupt processing flowchart an interrupt (maskable and non-maskable) processing program ends with a reti instruction. when this instruction is executed, the data previously stacked from the program counter pc and the register pair af are restored. after the cpu reads out the interrupt vector, the interrupt source acknowledges that the cpu accepts the request, and clears the request. a non-maskable interrupt cannot be disabled by programming. a maskable interrupt, on the other hand, can be enabled or dis- abled by programming. an interrupt enable ?p-?p (iff) is pro- vided on the bit 5 of register f in the cpu. the interrupt is enabled or disabled by setting iff to ??by the ei instruction or to ??by the di instruction, respectively. if is reset to ??by the reset operation or the acceptance of any interrupt (including non-maskable interrupt). the interrupt can be enabled after the subsequent instruction of ei instruction is executed. table 3.3 (1) lists the possible interrupt sources. 10/86 toshiba corporation tmp90c802a/803a table 3.3 (1) interrupt sources priority order type interrupt source vector value ? 8 vector value start address of general purpose interrupt processing start address of micro dma processing parameter 1 2 3 non maskable swi instruction nmi (input from nmi pin) intwd (watchdog) 02h 03h 04h 10h 18h 20h 0010h 018h 0020h 4 5 6 7 8 9 10 11 maskable into (external input 0) intto (timer 0) intt1 (timer 1) intt2 (timer 2) intt3 (timer 3) int1 (external input 1) intrx (end of serial receiving) inttx (end of serial transmission) 05h 06h 07h 08h 09h 0ah 0eh 0fh 28h 30h 38h 40h 48h 58h 70h 78h 0028h 0030h 0038h 0040h 0048h 0058h 0070h 0078h ff30h ff38h ff70h ff78h the ?riority order?in the table shows the order of the interrupt source to be acknowledge by the cpu when more than one interrupt are requested at one time. in interrupt of fourth and ?th orders are requested simultaneously, for example, an interrupt of the ?th?priority is acknowledged after a ?th?priority interrupt processing has been completed by a reti instruction. however, a lower priority interrupt can be acknowledged immediately by executing an ei instruction in a program that processes a higher priority inter- rupt. the internal interrupt controller merely determines the priority of the sources of interrupts to be acknowledged by the cpu when more than one interrupt are requested at a time. it is, therefore, unable to compare the priority of interrupt being exe- cuted with the one being requested. 3.3.2 micro dma processing figure 3.3 (3) is a ?w chart of the micro dma processing. parameters (addresses of source and destination, and transfer mode) for the data transfer between memories are loaded by the cpu from an address modi?d by an interrupt vector value. after the data transfer between memories according to these parameter, these parameters are updated and saved into the original locations. the cpu then decrements the number of transfers, and completes the micro dma processing unless the result is ?? if the number of transfer becomes ?? the cpu proceeds to the general purpose interrupt handling described in the previous chapter. toshiba corporation 11/86 tmp90c802a/803a figure 3.3 (3). micro dma processing flowchart the micro dma processing is performed by using only hardware to process interrupts mostly completed by simple data transfer. the use of hardware allows the micro dma processing to handle the interrupt in a higher speed that the conventional methods using software. the cpu registers are not affected by the micro dma processing. figure 3.3 (4) shows the functions of parameters used in the micro dma processing. 12/86 toshiba corporation tmp90c802a/803a figure 3.3 (4). parameters for micro dma processing parameters for the micro dma processing are located in the internal ram area (see table 3.3 (1) interrupt sources). the start address of each parameter is ?f00h + interrupt vec- tor value? from which a six bytes?space is used for the param- eter. this space can be used for any other memory purposes if the micro dma processing is not used. the parameters normally consist of the number of transfer, addresses of destination and source, and transfer mode. the number of transfer indicates the number of data transfer accepted in the micro dma processing. the amount of data transferred by a single micro dma processing is one or two bytes. the number of transfers is 256 when the number of transfers value is ?0h? both the destination and source addresses are speci?d by 2-byte data. the address space available for the micro dma processing ranges from 0000h to ffffh. bits 0 and 1 of the transfer mode indicates the mode updating the source and/or destination, and the bit 2 indicates the data length (one byte or two bytes). table 3.3 (2) shows the relation between the transfer mode and the result of updating the destination/source addresses. table 3.3 (2) addresses updated by micro dma processing transfer mode function destination address source address 000 001 010 011 100 101 110 111 1-byte transfer: fix the current source/destination addresses 1-byte transfer: increment the des tination address 1-byte transfer: increment the source address 1-byte transfer: decrement the source address 2-byte transfer: fix the current source/destination addresses 2-byte transfer: increment the destination address 2-byte transfer: increment the source address 2-byte transfer: decrement the source address 0 +1 0 0 0 +2 0 0 0 0 +1 -1 0 0 +2 -2 toshiba corporation 13/86 tmp90c802a/803a in the 2 byte transfer mode, data are transferred as follows: (destination address) ? (source address) (destination address + 1) ? (source address + 1) similar data transfers are made in the modes that ?ecrement the source address? but the updated address are different as shown in the table 3.3 (2). figure 3.3 (5) shows an example of the micro dma processing that handles data receiving of internal serial i/o. this is an example of executing ?n interrupt processing program after serial data receiving?after receiving 7-frame data (assume 1 frame = 1 byte for this example) and saving them into the memory addresses from ff00h to ff06h. call sioinit ; initial setting for serial addressing. set 1, (0ffe6h) ; enable an interrupt for serial data receiving. set 1, (0ffe8h) ; set the micro dma processing mode for the interrupt. ld (0ff7oh),7 ; set the number of transfer = 7 ldw (0ff71h), 0ff00h ; set ff00h for the destination address. ldw (0ff73h), 0ffebh ; set ffebh for the source (serial receiving buffer) address. ld (0ff75h),1 ; set the transfer mode (1-byte transfer:increment destination address.) ei : : org 0070h reti figure 3.3 (5). example of micro dma processing interrupt processing program after serial data receiving 14/86 toshiba corporation tmp90c802a/803a the bus operation in the general- purpose interrupt process- ing and the micro dma processing is shown in ?able 1.4 (2) bus operation for executing instructions?in the previous sec- tion. the micro dma processing time (when the number of transfer is not decremented to 0) is 46 states (9.2 m s at 10mhz oscillation frequency) without regard to the 1-byte/2-byte transfer mode. figure 3.3 (6) shows the interrupt processing ?wchart. figure 3.3 (6). interrupt processing flowchart toshiba corporation 15/86 tmp90c802a/803a 3.3.3 interrupt controller figure 3.3 (8) outlines the interrupt circuit. the left side of this ?ure represents an interrupt controller, and the right side comprises the cpu s interrupt request signal circuit and halt release signal circuit. the interrupt controller consists of interrupt request flip- ?ps, interrupt enable ?gs, and micro dma enable ?gs allo- cated to each of 14 channels. the interrupt request flip-?ps serve to latch interrupt requests from peripherals. each flip- ?p is reset to ??when a reset or interrupt is acknowledged by the cpu and the vector of the interrupt channel is read into the cpu, or when the cpu executes an instruction that clears an interrupt request flip-?p for the speci?d channel (write ?ector divided by 8?in the memory address ffc3h). for example, by executing. ld (ffc3h), 58h/8, the interrupt request flip-?ps for the interrupt channel ?nt1?whose vector is 58h is reset to?? the status of an interrupt request flip-?ps is found out by reading the memory address ffc2h or ffc3h. ??denotes there is not interrupt request, and ??denotes that an interrupt is requested. figure 3.3 (7) illustrates the bit con?uration indicating the status of interrupt request flip-?ps. figure 3.3 (7). con?uration of interrupt request flip-flops 16/86 toshiba corporation tmp90c802a/803a figure 3.3 (8). block diagram of interrupt controller the interrupt enable ?gs provided for all interrupt request channels are assigned to the memory address ffe6h to ffe7h. setting any of these ?gs to ??enables an interrupt of the respective channel. these ?gs are initialized to ??by resetting. clear the interrupt enable ?g in the di status. the micro dma enable ?g also provided for each interrupt request channel is assigned to the memory address ffe7h to ffe8h. the interrupt processing for each channel is placed in the micro dma processing mode by setting this ?g to ?? this ?g is initialized to 0?(general purpose interrupt processing mode) by resetting. figure 3.3 (9) shows the bit con?uration of the interrupt enable ?gs and micro dma enable ?gs. the external interrupt functions are shown below. toshiba corporation 17/86 tmp90c802a/803a interrupt common terminal mode how to set nmi falling edge int0 p80 level p8cr < edge> = 0 rising edge p8cr 18/86 toshiba corporation tmp90c802a/803a figure 3.3 (9). interrupt/micro dma enable flags toshiba corporation 19/86 tmp90c802a/803a 3.4 standby function when a halt instruction is executed, the tmp90c802 selects one of the following modes as determined by the halt mode set register: (1) run: suspends only the cpu operation. the power consumption remains unchanged. (2) idle1: suspends all internal circuits except the inter nal oscillator. in this mode, the power con sumption is less than 1/10 of that in the normal operation. (3) idle2: operate only the internal oscillator and speci? internal i/o devices. the power consumption is about 1/3 of that in the normal operation. (4) stop: suspends all internal circuits including the internal oscillator. in this mode, the power consumption is considerably reduced. the halt mode set register wdmod 20/86 toshiba corporation tmp90c802a/803a 3.4.1 run mode figure 3.4 (2) shows the timing for releasing the halt state by interrupts in the run/idle 2 mode. in the run mode, the system clock in the mcu continues to operate even after a halt instruction is executed. only the cpu stops executing the instruction. until the halt state is released, the cpu repeats dummy cycles. in the halt state, an interrupt request is sampled with the rising edge of the ?lk?signal. figure 3.4 (2). timing chart for releasing the halt state by interrupts in run/idle 2 modes toshiba corporation 21/86 tmp90c802a/803a 3.4.2 idle 1 mode figure 3.4 (3) illustrates the timing for releasing the halt state by interrupts in the idle 1 mode. in the idle 1 mode, only the internal oscillator and the watchdog timer operate. the system clock in the mcu stops, and the clk signal is ?ed at the ??level. in the halt state, an interrupt request is sampled asyn- chronously with the system clock, however the halt release (restart of operating) is performed synchronously with it. note: an interrupt requested by the watchdog timer is prohibited through the halt period in this mode. figure 3.4 (3). timing chart of halt released by interrupts in idle1 mode 3.4.3 idle 2 mode figure 3.4 (2) shows the timing of halt release caused by interrupts in the run/idle 2 mode. in the idle 2 mode, the halt state is released by an interrupt with the same timing as in the run mode, except the internal operation of the mcu. in the run mode, only the cpu stops executing the current instruction, and the system clock is supplied to all internal devices. in the idle 2 mode, however, the system clock is supplied to only speci? internal i/o devices. as a result, the halt state in the idle 2 mode requires only a 1/3 of the power consumed in the run mode. in the idle 2 mode, the system clock is supplied to the following i/o devices: 8-bit timer serial interface watchdog timer 3.4.4 stop mode figure 3.4 (4) is a timing chart for releasing the halt state by interrupts in the stop mode. the stop mode is selected to stop all internal circuits including the internal oscillator. in this mode, all pins except special ones are put in the high-impedance state, independent of the internal operation of the mcu. table 3.4 (1) summarizes the state of these pins in the stop mode. note, however, that the pre-halt state (the status prior to execution of halt instruction) of all output pins can be retained by setting the internal i/o register wdmod 22/86 toshiba corporation tmp90c802a/803a figure 3.4 (4). timing chart of halt released by interrupt in stop mode the internal oscillator can be also restarted by the input of the reset signal at ??the cpu. in the reset restart mode, however, the warming-up counter remains inactive in order to get the quick response of mcu when the power is turned on (power on reset). as a result, the normal operation may not be performed due to the unstable clock supplied immediately after restarting the internal oscillator. to avoid this, it is necessary to keep the reset signal at ??long enough too release the halt state in the stop mode. toshiba corporation 23/86 tmp90c802a/803a table 3.4 (1) state of pins in stop mode in/out drve = 0 drve = 1 p0 input mode output mode out out p1 input mode output mode in out p2 input mode output mode in out p3 input pin output pin in out p80 (int0) p81 (int1) input pin input pin in in in* nmi clk reset x1 x2 input pin output pin input pin input pin output pin in in ? in ? in ? in: the input gate is operating. fix the input voltage at either ??or ??to prevent the pin ?ating. out: the output status. it is necessary to leave int0 at ??until the second bus cycle of the interrupt response sequence is completed, when the stop mode is released by the level mode of int0. o: can be used to release the halt command. ? cannot be used to release the halt command. table 3.4 (2) i/o operation during halt and how to release the halt command halt mode run idle2 idle1 stop wdmod 24/86 toshiba corporation tmp90c802a/803a 3.5 function of ports the tmp90c802 contains total 32 pins input/output ports. these ports function not only for the general-purpose i/o but also for the input/output of the internal cpu and i/o. table 3.5 describes the functions of these ports. table 3.5 functions of ports port name pin name no. of pins direction direction set unit resetting value pin name for internal function port 0 p00 ~ p07 8 i/o byte input d0 ~ d7 port 1 p10 ~ p17 8 i/o byte input a0 ~ a7 port 2 p20 ~ p27 8 i/o bit input a8 ~ a15 port 3 p31 p32 p33 p35 p36 p37 1 1 1 1 1 1 input output output output output input input output output output output input rxd sclk txd rd wr wait /to1 port 8 p80 p81 1 1 input input input input int0 int1/ti2 these port pins function as the general-purpose input/output ports by resetting. the port pins, for which input or output is programmably selectable, function as input ports by resetting. a separate program is required to use them for an internal function. the TMP90C803A functions in the same way as the tmp90c802a except: port 0 always functions as data bus (d0 to d7) port 0 always functions as address bus (a0 to a7) port 0 always functions as address bus (a8 to a15) p35 and p36 of always functions as data rd and wr pins, respectively. toshiba corporation 25/86 tmp90c802a/803a 3.5.1 port 0 (p00 ~ p07) port 0 is an 8-bit general-purpose i/o port p0 whose i/o func- tion is speci?d by the control register p01cr 26/86 toshiba corporation tmp90c802a/803a 3.5.2 port 1 (p10 ~ p17) port 1 is an 8-bit general-purpose i/o port p1 whose i/o func- tion is speci?d by the control register p01cr toshiba corporation 27/86 tmp90c802a/803a figure 3.5 (3). registers for port 0 and 1 28/86 toshiba corporation tmp90c802a/803a 3.5.3 port 2 (p20 ~ p27) port 2 is an 8-bit general-purpose i/o port p2 whose i/o func- tions are speci?d by the control register p2cr for each bit. all bits of the output latch and the control register are initialized to ?? by resetting, where by port 2 turns to the input mode. in addition to the general-purpose i/o port function, it functions as an address bus (a8 ~ a15). the address bus function can be selected by setting the register p01cr toshiba corporation 29/86 tmp90c802a/803a figure 3.5 (5). registers for port 2 30/86 toshiba corporation tmp90c802a/803a 3.5.4 port 3 (p30 ~ p33, p35 ~ p37) port 3 is an 6-bit general-purpose i/o port p3 with ?ed i/o func- tion. all bits of the output latch are initialized to ??by resetting, and ?igh level?is generated to the output port. in addition to the i/o port function, p31 ~ p31 have the i/o function for the internal serial interface, while p35 ~ p37 have the external memory control function. the additional functions can be selected by the control register p3cr. all bits of the control register are initialized by ??by resetting, and the port turns to the general-purpose i/o ports mode. however, p37 is placed in the input mode after resetting, and turns to the to1 output port mode after writing p3c toshiba corporation 31/86 tmp90c802a/803a figure 3.5 (7). register for ports 3 32/86 toshiba corporation tmp90c802a/803a 3.5.5 port 8 (p80 ~ p81) port 8 is a 2-bit general-purpose input port p8. port 8 also has the functions of interrupt request input, clock input for a timer/event counter. (1) p80/int0 p80 is a general-purpose input port, also used as the external interrupt request input pin int0. int0 allows the selection of either an ??level interrupt or rising edge interrupt by using the control register p8cr toshiba corporation 33/86 tmp90c802a/803a figure 3.5 (10). registers for port 8 3.6 timers the tmp90c802a incorporates four 8-bit timers. the four 8-bit timers can be operated independently, and can also be functioned as two 16-bit timer by mode setting: timer 2 has an event counter function, so that it can also be used as an 8-bit counter. furthermore, it can be used as a 16- bit counter cascaded with timer 3. 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) 8-bit programmable pulse generation (ppg) output mode (timer 0 and timer 1) 8-bit pwm output mode (timer 1) possible arrangements: 8-bit x 2 and 16-bit x 1 8-bit event counter mode (timer 2) 16-bit event counter mode (timer 2 and timer 3) software counter latch function (timer 2 and timer 3) 3.6.1 8-bit timers the tmp90c802a incorporates four 8-bit interval timers (tim- ers 0, 1, 2 and 3), each of which can be operated indepen- dently. the cascade connection of timer 0 and 1, or timer 2 and 3 allows these timers used as 16-bit internal timers. figure 3.6 (1) is a block diagram of the 8-bit timers (timer 0 and timer 1). figure 3.6 (2) is a block diagram of the 8-bit timer/event counters (timer 2 and timer 3). each interval timer is composed of an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register, with a timer flip- ?p (tff1) provided to each pair of timer 0/1. internal clocks (?1, ?16 and ?256), some of the input clock sources for the interval timers, are generated by the 9-bit prescaler shown in figure 3.6 (3). their operating modes of the 8-bit timers and ?p-?ps are controlled by four control registers (tclk, tffcr, tmod and trun). 34/86 toshiba corporation tmp90c802a/803a figure 3.6 (1). block diagram of 8-bit timers (timer 0 and 1) figure 3.6 (2). block diagram of 8-bit timer/counter (timer 2 and timer 3) toshiba corporation 35/86 tmp90c802a/803a prescaler an 9-bit prescaler is provided to further devide the clock fre- quency already divided to a 1/4 of the frequency of the source clock (fc). it generates an input clock pulse for the 8-bit timers, 16- bit timer/event counter, the baud-rate generator, etc. for the 8-bit timers, three types of clock are generated (?1, ?16 and ?256). the prescaler can be run or stopped by using the 5th bit trun 36/86 toshiba corporation tmp90c802a/803a up-counter this is an 8-bit binary counter that counts up by an input clock pulse speci?d by an 8-bit timer clock control register tclk and an 8-bit timer mode register (tmod). the input clock pulse for timer 0 and 2 is selected from ?1, ?16 and ?256 according to the setting of the tclk register. when using timer 2 as the counter, set bit 4 and bit 5 of tclk to ?? example: when setting tclk toshiba corporation 37/86 tmp90c802a/803a figure 3.6 (4). 8-bit timer mode register tmod 38/86 toshiba corporation tmp90c802a/803a figure 3.6 (5). 8-bit timer clock control register tclk toshiba corporation 39/86 tmp90c802a/803a figure 3.6 (6). timer/serial channel control registers trun 40/86 toshiba corporation tmp90c802a/803a figure 3.6 (7). 8-bit timer flip-flop control register (tffcr) toshiba corporation 41/86 tmp90c802a/803a a timer registers note: only for writing. 8-bit registers are provided to set the interval time. when the set value of a timer register matches that of an up-counter, the match signal of their comparators turn to the active mode. if ?0h?is set, this signal becomes active when the up-counter over?ws. the values of the timer register 0 and timer register 1 cannot be read. the values of the timer register 2 and timer register 3, however, can be read because these registers are assigned same address with the counter latch registers. when the values of these registers are read, they become the values of the counter latch registers (read only registers). when the values of these registers are written, they become the values of the values of the values of the timer registers (write only register). ? comparators a comparator compares the values in an up-counter and a timer register. when they matches, the up- counter is cleared to ?? and an interrupt signal (inttn) is generated. if the timer flip-?p inversion is enabled by the timer flip-?p control register, the timer flip-?p is inverted. ? timer flip-?p (timer f/f) the status of the timer flip-?p is inverted by the match signal (output by comparator) of each interval timer. its status can be output to the timer output pin to1 (also used as p37). this timer f/f is provided to the timer pair, timer 0 - timer 1 is called tff1. the status of tff1 is output to to1. the timer f/f are controlled by a timer flip-?p control register (tffcr). ?tffcr 42/86 toshiba corporation tmp90c802a/803a use the following table for selecting the input clock: table 3.6 (1) 8-bit timer interrupt cycle and input clock interrupt cycle @fc = 10mhz resolution input clock 0.8 m s ~ 204 m s 12.8 m s ~ 3.264ms 204.8 m s ~ 52.429ms 0.8 m s 12.8 m s 204.8 m s ?1 (8/fc) ?16 (128/fc) ?256 (2048/fc) generating pulse at 50% duty the timer flip-?p is inverted at speci?d intervals, and its status is output to a timer output pin to1 (only timer 0, timer 1). example: to output pulse from to1 at fc = 10mhz every 4.8 m s, the registers should be set as follows: this example uses timer 1, but the same operation can be effected by using timer 0. figure 3.6 (8). pulse output (50% duty) timing chart toshiba corporation 43/86 tmp90c802a/803a a making timer 1 count up by match signal from timer 0 comparator. select the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. figure 3.6 (9) ? software inversion the timer flip-?ps can be inverted by software independent of the timer operation. writing ?, 0?into the bits tffcr 44/86 toshiba corporation tmp90c802a/803a the lower eight bits of the timer (interrupt) cycle is set by treg0 and the upper eight bits of that is set by treg1. note that treg0 must be always set ?st (writing data into treg0 disables the comparator temporarily, which is restarted by writ- ing data into treg1). example: to generate interrupts intt1 at fc = 8mhz every 1 second, the timer registers treg0 and treg1 should be set as follows: as ?16 (= 16 m s @ 8mhz) is selected as the input clock, 1 sec/16 m s = 62500 = f424h therefore, treg1 = f4h treg0 = 24h the match signal is generated by timer 0 comparator each time the up-counter uc0 matches treg0. in this case, the up-counter uco is not cleared, but the interrupt intt0 is generated. timer 1 comparator also generates the match signal each timer the up-counter uc1 match treg1. when the match sig- nal is generated simultaneously from comparators of timer 0 and timer 1, the up-counters uc0 and uc1 are cleared to ?? and the interrupt intt1 is generated. if the timer flip-?p inversion is enabled by the timer flip-?p control register, the timer flip-?p tff1 is inverted at the same time. example: given treg1 = 04h and treg0 = 80h, figure 3.6 (10) timer 0 timer 1 intt0 to1 match intt1 to1 match 16-bit timer mode (count-up timer 1 by verflow of timer 0) interrupt is generated. can't output (to1 can? be output the matching with treg0) treg0 (continue counting when match) interrupt is generated. can output *can output the matching with both treg0 and treg1) treg1 * 2 8 + treg0 (16 bit) (cleared by matching with both registers.) 8-bit timer mode (count-up timer 1 by matching of timer 0) interrupt is generated. can output (timer 0 or timer 1) treg0 (clear when match) interrupt is generated. can output (timer 0 or timer 1) treg1*treg0 (multiplied valve) (cleared by matching) (3) 8-bit ppg (programmable pulse generation) mode pulse can be generated at any frequency and duty rate by timer 1 or timer 3. the output pulse may be either low-or high-active. in this mode, timers 0 cannot be used. pulse is output to to1 (shared with p37). toshiba corporation 45/86 tmp90c802a/803a following is the timing of timer 1 in the 8-bit ppg mode, programmable pulse is generated by the inversion of the timer output put each time the 8 bit up- counter 1 (uc1) matches the timer register treg0 or treg1. note that the set value of treg0 must be smaller than that of treg1. in this mode, the up-counter uc0 of timer 0 cannot be used (set trun 46/86 toshiba corporation tmp90c802a/803a figure 3.6 (11). block diagram of 8-bit ppg mode example: generate pulse at 50khz and 1/4 duty rate (@fc = 8mhz) calculate the set value of the timer registers. to obtain the frequency of 50khz, the pulse cycle should be: 1/50khz = 20 m s. given ?1 = 1 m s (@ 8mhz), 20 m s/1 m s = 20 consequently, the timer register 1 (treg1) should be set to 20 =14h. given a 1/4 duty, t x 1/4 = 20 x 1/4 = 5 m s 5 m s/1 m s = 5 as a result, the timer register 0 (treg0) should be set to 5 = 05h. toshiba corporation 47/86 tmp90c802a/803a precautions for ppg output by rewriting the content of the treg (timer register), it is possible to make tmp90c802 output ppg. however, be careful, since the timing to rewrite treg differs depending on the pulse width of ppg to be set. this problem is explained below by an example. example: to output ppg through 8 bit timers 0 and 1 treg0: pulse width treg1: cycle the pulse width is normally changed by the interrupt (intt1) process routine in each cycle. however, when the pulse width to be set (the value to be written in treg0) is small, trouble may occur, in that the timer counter exceeds the value of treg0 before the interrupt process routine is set. therefore, it is recommended to make the following decisions in intt0 and intt1 interrupt processes. intt0 process routine: the value of treg0 is rewritten only when the value to be written in treg0 is smaller than the current value of treg0. intt1 process routine: on the contrary to intt0, treg0 is written only when the value to be written in treg0 is larger than the current value of treg0. tmp90c802 cannot read the content of treg, so it is necessary to buffer the content of treg in a ram (or the like) for making the above judgement. 4) 8-bit pwm (pulse width modulation) mode this mode is only available for timer 1 and can output 8-bit resolution pwm. it is output to to1 (also used as p37). timer 0 can be used as 8-bit timers. the inversion of the timer output occurs when the up- counter (uc1) matches the set value of the timer register treg1, as well as when an over?w of 2 n - 1 (n = 6, 7 or 8 selected by tmod 48/86 toshiba corporation tmp90c802a/803a figure 3.6 (12). block diagram of 8-bit pwm mode example: generate the following pwm to the to1 pin at fc = 10mhz. assuming the pwm cycle is 50.4 m s when ?1 = 0.8 m s and @fc = 10mhz, 50.4 m s/0.8 m s = 63 = 2 6 - 1 consequently, n should be set at 6 (tmod1 toshiba corporation 49/86 tmp90c802a/803a precautions for pwm output tmp90c802 can output pwm by the 8-bit timer. however, changing the pulse width of pwm requires special care. this problem is explained by the following example. example: to output pwm by 8-bit timer treg1: pulse width cycle: fixed (2 6 - 1, 2 7 - 1, 2 8 - 1) table 3.6 (3) pwm cycle and selection of 2 n - 1 counter expression pwm cycle (@fc = 10mhz) ?1 (8/fc) ?16 (128/fc) ?256 (2048/fc) 2 6 - 1 (2 6 - 1) x ?n 50.4 m s 8064 m s 12.9ms 2 7 - 1 (2 7 - 1) x ?n 101.6 m s 1625.6 m s 26.0ms 2 8 - 1 (2 8 - 1) x ?n 204.0 m s 3264.0 m s 52.2ms 50/86 toshiba corporation tmp90c802a/803a in the pwm mode, intt1 occurs at the coincidence with treg1. however, the pulse width cannot be changed directly using the interrupt. (depending on the value of treg1 to be set, coincidence with treg1 may be detected again in a single cycle, inverting the timer output.) to eliminate this problem in changing the pulse width, it is effective the halt the timer with the intt1 process, modify the value of treg1, set the timer output to ?? and restart the timer. in the mean time, the output waveform loses shape when the pulse width is changed. this method is valid for a system that allows a deformed output waveform. (5) a table of all timer mode table 3.6 (4) timer mode register tmod tclk tffcr bit symbol t10m (t32m) pwm1 (pwm1) t1clk (t3clk) t0clk (t2clk) ff1is (ff1is) function timer mode pwm cycle upper input lower input inversion select 16-bit timer mode 01 ?1, 16, 256 (01, 10, 11) 1(*) 8-bit timer x 2ch 00 comparator output from lower timer, ?1, 16, 256 (00, 01, 10, 11) ?1, 16, 256 (01, 10, 11) 0: lower timer 1: upper timer table 3.6 (4) timer mode register tmod tclk tffcr bit symbol t10m (t32m) pwm1 (pwm1) t1clk (t3clk) t0clk (t2clk) ff1is (ff1is) function timer mode pwm cycle upper input lower input inversion select 8-bit ppg x 1ch 10 ( table 3.6 (4) time r register tmod bit symbol t10m (t32m) pwm1 (pwm1) t1 c function timer mode pwm cycle u p (note) ? don t care *: it is possible to set to ?? when timer f/f is not used. 3.6.2 8-bit timer/event counter (1) event counter mode timer 2 has the 8-bit timer/event counter and can be used not only as the 8-bit timer but also as the counter. timer 2 can be placed in the event counter mode by setting the input clock of timer 2 as the external count input t12. timer 2 and timer 3 can be used as an 8-bit counter and an 8-bit timer, respectively, and as a 16-bit counter through cascade con- 8-bit pwm x 1ch 11 2 6 - 1, 2 7 - 1, 2 8 - 1 (01, 10, 11) ?1, 16, 256 (01, 10, 11) ? 8-bit timer x 1ch ?1, 16, 256 (01, 10, 11) impossible to output table 3.6 (4) timer mode register tmod tclk tffcr bit symbol t10m (t32m) pwm1 (pwm1) t1clk (t3clk) t0clk (t2clk) ff1is (ff1is) function timer mode pwm cycle upper input lower input inversion select toshiba corporation 51/86 tmp90c802a/803a nection. the counter is incremented at the rising edge of the counter input ti2. the counter input pin ti2 is also used for p81/int1 and has the zero-cross detec- tion function. to use this pin as the counter input (ti2), set tclk 52/86 toshiba corporation tmp90c802a/803a toshiba corporation 53/86 tmp90c802a/803a the latched counter value can be read by reading timer register 2. 3.7 serial channel the tmp90c802a incorporates a serial i/o channel for full duplex asynchronous transmission (uart) and i/o expansion. the serial channel has the following operating modes: the mode 3 accommodates a wake-up function to start the slave controllers in a controller serial link (multi-controller system). figure 3.7 (1) shows the data format (1-frame data) in each mode. figure 3.7 (1). data formats data received and transmitted are stored temporarily into separate buffer registers to allow independent transmission and receiving (full-duplex). in the i/o interface mode, however, the data transfer is half-duplex due to the single sclk (serial clock) pin is used for trans- mission and receiving. the pin function (port function or serial i/o function) is selected by the port 3 control register. for example, p31 can be used as the rxd pin by setting p3cr 54/86 toshiba corporation tmp90c802a/803a in the uart mode, a check function is added not to start the receiving operation by error start bits due to noise. the channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings. when a request is issued to the cpu to transmit data after the transmitting buffer becomes empty or to read data after the receiving buffer completed to store data, the interrupt inttx or intrx occurs respectively, in receiving data, the occurrence of an overrun error, parity error or framing error sets the ?g sccr toshiba corporation 55/86 tmp90c802a/803a figure 3.7 (2). serial channel mode register figure 3.7 (3). serial channel control register figure 3.7 (4). serial transmission/receiving buffer register 56/86 toshiba corporation tmp90c802a/803a figure 3.7 (5). timer/serial channel operation control register toshiba corporation 57/86 tmp90c802a/803a figure 3.7 (6). port 3 control register 3.7.2 architecture figure 3.7 (7) is a block diagram of the serial channel. 58/86 toshiba corporation tmp90c802a/803a figure 3.7 (7). block diagram of serial channel toshiba corporation 59/86 tmp90c802a/803a baud-rate generator the baud-rate generator comprises a circuit that generates a clock pulse to determine the transfer speed for transmission/receiving in the asynchronous communica- tion (uart) mode. the input clock to the baud-rate generator ?t4(fc/32), ?t16 (fc/128), ?t64 (fc/512) or ?t256 (fc/2048) is generated by the 9-bit prescaler. one of these input clocks is selected by the timer/serial channel control register trun 60/86 toshiba corporation tmp90c802a/803a the receiving counter is a 4-bit binary counter used in the asynchronous communication (uart) mode and is counted by using sioclk. 16 pulses of sioclk is used for receiving 1-bit data. the data are sampled three tim- ers at the 7th, 8th and 9th pulses and evaluated by the rule of majority. for example, if data sampled at the 7th, 8th and 9th clock are ?? ??and ?? the received data is evaluated as ?? the sampled data ?? ??and ??is evaluated that the received data is ?? ? receiving control 1) i/o interface mode the rxd signal is sampled on the rising edge of the shift clock which is output to the sclk pin. 2) asynchronous communication (uart) mode the receiving control features a circuit for detecting the start bit by the rule of majority. when two or more 0 are detected during 3 samples, it is recognized as normal start bit and the receiving operation is started. data being received are also evaluated by the rule of majority. ? receiving buffer the receiving buffer has a double-buffer structure to prevent overruns. received data are stored into the receiving buffer 1 (shift register type) for each 1 bit. when 7 or bits data are stored in the receiving buffer 1, the stored data is transferred to the receiving buffer 2 (scbuf), and the interrupt intrx occurs at the same time. the cpu reads out the receiving buffer 2 (scbuf). data can be stored into the receiving buffer 1 before the cpu reads out the receiving buffer 2 (scbuf). note, however, that an overrun occurs unless the cpu reads out the receiving buffer 2 (scbuf) before the receiving buffer 1 receiving all bits of the next data. when an overrun occurred, the data in the buffer 2 and sccr toshiba corporation 61/86 tmp90c802a/803a clk, and a transmission shift clock txdsft is gener- ated. ? transmission buffer the transmission buffer scbuf shifts out the data written by the cpu from the lsb as based on the shift clock txdsft (same period as tcdclk) generated by the transmission control unit. when all bits are shifted out, the transmission buffer becomes empty, generating the interrupt inttx. error ?ag there error ?ags are prepared to increase the reliability of received data. 1) overrun error (sccr 62/86 toshiba corporation tmp90c802a/803a 3.7.3 operation (1) mode 0 (i/o interface mode) this mode is used to increase the number of i/o pins of the tmp90c802a. the tmp90c802a supplies the transmitting/receiving data and synchronous clock (sclk) to n external shift register. interrupt timing of transmitting figure 3.7 (8). i/o interface mode transmission each timer the cpu writes data into the transmission buffer, 8-bit data are output form txd pin. when all data are output, irfh toshiba corporation 63/86 tmp90c802a/803a figure 3.7 (9). transmitting operation (i/o interface mode) example: when transmitting data from p33 pin, the control registers should be set as described below. receiving each time the cpu reads the receiving data and clears the receiving interrupt ?ag irfh 64/86 toshiba corporation tmp90c802a/803a (2) mode 1 (7-bit uart mode) the 7-bit uart mode is selected by setting the serial channel mode register scmod toshiba corporation 65/86 tmp90c802a/803a (3) mode 2 (8-bit uart mode) the 8-bit uart mode is selected by setting scmod 66/86 toshiba corporation tmp90c802a/803a figure 3.7 (11). serial link using wake-up function protocol 1) select the 9-bit uart mode for the master and slave controllers. 2) set the scmod toshiba corporation 67/86 tmp90c802a/803a receiving to the master controller by this transmission. example: link two slave controllers serially with the master controller, and use the internal clock ? (fc/2) as the transfer clock. set the master control set the slave 2 (note) x: don t care -: no change 3.8 watchdog timers (runaway detecting timer) when the malfunction (runaway) of the cpu occurs due to any cause such as noise, the watchdog timer (wdt) detects it to r eturn to the normal state. when wdt has detected malfunction, a non-maskable interrupt is generated to indicate it to the cpu. 3.8.1 architecture 68/86 toshiba corporation tmp90c802a/803a figure 3.8 (1) is a block diagram of the watchdog timer (wdt). the watchdog timer consists of a 20-stage binary counter (input clock: @fc/2), a ?p-?p that disables/enables the selector, a selector that selects one of the four output clocks generated from the binary counter, and two control registers. the watchdog timer generates intwd (watchdog timer interrupt) after a time speci?d by the register wdmod toshiba corporation 69/86 tmp90c802a/803a 70/86 toshiba corporation tmp90c802a/803a figure 3.8 (2). watchdog timer mode register toshiba corporation 71/86 tmp90c802a/803a figure 3.8 (3). watchdog timer control register 3.8.3 operation (1) watchdog timer mode register (wdmod) set the detecting timer of watchdog timer wdmod 72/86 toshiba corporation tmp90c802a/803a 2) set 2 16 /fc for the detecting time of watchdog timer. 3) disable the watchdog timer. 4) select the idle 2 mode. 5) select the stop mode (warming-up time 2 16 /fc). 4. electrical characteristics tmp90c802ap/tmp90c802am 4.1 absolute maximum ratings symbol parameter rating unit v cc supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 85 c) 250 mw t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p8 -0.3 0.3v cc v v il2 reset , int0, nmi -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3, p8 0.7v cc v cc + 0.3 v v ih2 reset , int0, nmi 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v toshiba corporation 73/86 tmp90c802a/803a note: i dar is guaranteed for a total of up to 8 optional ports. v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) (note) -1.0 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 1 idle 2 17 (typ) 1.5 (typ) 6 (typ) 30 5 15 ma ma ma fosc = 10mhz (25%up @12.5mhz) stop (ta = -40 ~ 85 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 50 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) 2 ram back up 6v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , nmi ,int0 0.4 1.0 (typ) v 4.3 ac characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t osc osc. period = x 80 1000 100 80 ns t cyc clk period 4x 4x 400 320 ns t wl clk low width 2x - 40 160 120 ns t wh clk high width 2x - 40 160 120 ns t ac address setup to rd , wr x - 45 55 35 ns t rr rd low width 2.5x - 40 210 160 ns t ca address hold time after rd , wr 0.5x - 30 20 10 ns t ad address to valid data in 3.5x - 95 255 185 ns t rd rd to valid data in 2.5x - 80 170 120 ns t hr input data hold after rd 0 0? ns t ww wr low width 2.5x - 40 210 160 ns t dw data setup to wr 2x - 50 150 110 ns t wd data hold after wr 30 90 30 90 30 90 ns t cwa rd , wr to valid wait 1.5x - 100 50 20 ns t awa address to valid wait 2.5x - 130 120 70 ns t was wait setup to clk 70 70 70 ns t wah wait hold after clk 0 0? ns t rv rd , wr recovery time 1.5x - 35 115 85 ns t cpw clk to port data output x + 200 300 280 ns 4.2 dc characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter min max unit test conditions 74/86 toshiba corporation tmp90c802a/803a ac output level high 2.2v/low 0.8v ac input level high 2.4v/low 0.45v (d0 ~ d7) high 0.8v cc /low 0.2v cc (excluding d0 ~ d7) t prc port data setup to clk 200 200 200 ns t cpr port data hold after clk 100 100 100 ns t chcl rd /wr hold after clk x - 60 40 20 ns t clc rd /wr setup to clk 1.5x - 50 100 70 ns t clha address hold after clk 1.5x - 80 70 40 ns t acl address setup to clk 2.5x - 80 170 120 ns t cld data setup to clk x - 50 50 30 ns 4.4 zero-cross characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 vac p - p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.3 ac characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max toshiba corporation 75/86 tmp90c802a/803a 4.5 serial channel timing-i/o interface mode v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12mhz clock unit min max min max min max t scy serial port clock cycle time 8x 800 640 ns t oss output data setup sclk rising edge 6x - 150 450 330 ns t ohs output data hold after sclk rising edge 2x - 120 80 40 ns t hsr input data hold after sclk rising edge 0 0? ns t srd sclk rising edge to input data valid 6x - 150 450 330 ns 4.6 8-bit event counter v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12mhz clock unit min max min max min max t vck ti2 clock cycle 8x + 100 900 740 ns t vckl ti2 low clock pulse width 4x + 40 440 360 ns t vckh ti2 high clock pulse width 4x + 40 440 360 ns 76/86 toshiba corporation tmp90c802a/803a 4.7 interrupt operation v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 10mhz clock unit min max min max min max t intal nmi , int0 low level pulse width 4x 400 320 ns t intah nmi , int0 high level pulse width 4x 400 320 ns t intbl int1, int2 low level pulse width 8x + 100 900 740 ns t intbh int1, int2 high level pulse width 8x + 100 900 740 ns toshiba corporation 77/86 tmp90c802a/803a 4.8 i/o interface mode timing 78/86 toshiba corporation tmp90c802a/803a 4.9 timing chart 5. table of special function registers the special function registers include the i/o ports, peripheral control registers allocated to the 48-byte addresses from ffc0h to ffefh. toshiba corporation 79/86 tmp90c802a/803a note: read/write r/w: either read or wirite is possible r: only read is possible. w: only write is possible. prohibit rmw: prohibit read modify write (prohibit res/set instruction etc.) tmp90c802 special function register address list address symbol address symbol address symbol ffc0 ffc1 ffc2 ffc3 ffc4 ffc5 ffc6 ffc7 ffc8 ffc9 ffca ffcb ffcc ffcd ffce ffcf p0 p1 p01cr (irfl) irfh p2 p2cr p3 p3cr ffd0 ffd1 ffd2 ffd3 ffd4 ffd5 ffd6 ffd7 ffd8 ffd9 ffda ffdb ffdc ffdd ffde ffdf p8 p8cr wdmod wdcr treg0 treg1 treg2 treg3 tclk tffcr tmod trun ffe0 ffe1 ffe2 ffe3 ffe4 ffe5 ffe6 ffe7 ffe8 ffe9 ffea ffeb ffec ffed ffee ffef intel inteh (dmael) dmaeh scmod sccr scbuf (1) i/o port msb lsb symbol name address 7 6 5 4 3 2 1 0 p0 port 0 0ffc0h p07 p06 p05 p04 p03 p02 p01 p00 r/w input mode p1 port 1 0ffc1h p17 p16 p15 p14 p13 p12 p11 p10 r/w input mode p2 port 2 0ffc4h p27 p26 p25 p24 p23 p22 p21 p20 r/w input mode p3 port 3 0ffc6h p37 p36 p35 p33 p32 p31 r r/w r/w r/w r/w r input 1 1 1 1 input p8 port 8 0ffd0h p81 p80 ?r input modei (2) i/o port control msb lsb symbol name address 76543 2 1 0 p01cr (irfl) port 01/ control reg. 0ffc2h prohibit rmw irf0 irft0 irft1 ext p1c p0c ? www 000 0 0 0 interrupt request flag 1 : interrupt being requested p1, p2 control o : i/o port 1 : address bus p1 control 0 : in 1 : out p0 control 0 : in 1 : out 80/86 toshiba corporation tmp90c802a/803a p2cr port 2 control reg. 0ffc5h prohibit rmw p27c p26c p25c p24c p23c p22c p21c p20c w 00000 0 0 0 (2) i/o port control msb lsb symbol name address 76543 2 1 0 p3cr port 3 control reg. 0ffc7h waitc1 waitc0 rde r/w r/w 000 wait control 00 : 2state wait 01 : normal wait 10: non wait 11: timer0/1 output rd control 0 : rd for only external access 1 : always rd p 3 c o 0 1 (2) i/o port control msb symbol name address 7 6 5 symbol in ( ) denotes another name. p8cr port 8 control reg. 0ffd1h prohibit rmw zce1 edge ?w ?0 *int1/ti2 control 1 : zcd enable int0 control 0 : level 1 : edge (3) watchdog timer control msb lsb symbol name address 7654 3 2 1 0 wdmod watch dog timer mode reg. 0ffd2h wdte wdtp1 wdtp0 warm haltm1 haltm0 exf drve r/w r/w r/w r/w r r/w 1000 0 0 unde?ed 0 1 : wdt enable wdt detecting time 00 : 2 14 /fc 01 : 22 16 /fc 10 : 2 18 /fc 11 : 2 20 /fc warming up time 0 : 2 14 /fc 1 : 2 16 /fc standby mode 00 : run mode 01 : stop mode 10 : idle1 mode 11 : idle2 mode invert each time exx instruction is executed 1 : to drive pin in stop mode wdcr watch dog timer mode reg. 0ffd3h prohibit rmw w b1h : wdt disable code 4eh : wdt clear code (4) timer/event counter control msb lsb symbol name address 7654 3210 treg0 8bit timer register 0 0ffd4h prohibit rmw w unde?ed treg1 8bit timer register 1 0ffd5h prohibit rmw w unde?ed treg2 8bit timer register 2 0ffd6h prohibit rmw r/w r: counter latch register 2, w: *bit timer register 2 unde?ed (2) i/o port control msb lsb symbol name address 76543 2 1 0 toshiba corporation 81/86 tmp90c802a/803a note: 00: 8bit timer x 2 or 8bit counter + 8bit timer 01: 16bit timer or 16bit counter treg3 8bit timer register 3 0ffd7h prohibit rmw r/w r: counter latch register 3, w: *bit timer register 3 unde?ed tclk 8bit timer source clock control reg. 0ffd8h t3clk1 t3clk0 t2clk1 t2clk0 t1clk1 t1clk0 t0clk1 t0clk0 r/w r/w r/w r/w 0000 0000 8bit 00 : to2trg 01 : ?1 10 : ?16 11 : ?256 00: 01 : ?1 10 : ?16 11 : ?256 (8bit mode only) 8bit 00 : to0trg 01 : ?1 10 : ?16 11 : ?256 00 : 01 : ?1 10 : ?16 11 : ?256 (8bit mode only) tffcr 8bit timer flip-flop control reg. 0ffd9h latch tff1c1 tff1c0 tff1ie tff1is w w r/w 1 0 0 0 : latch (one shot) 00 : clear tff1 01 : set tff1 10 : invert tff1 11 : don? care 1 : tff1 invert enable 0 : invert by 8bit timer 0 1 : invert by 8-bit timer 1 tmod 8bit timer mode reg. 0ffdah t23m1 t23m0 t10m1 t10m0 pwm01 pwm00 r/w r/w r/w 00 0000 (note) 00 : 8bit timer/counter 01 : 16bit timer/counter 10 : don? care 11 : don? care 00: 8bit timer 01: 16bit timer 10: 8bit ppg 11: 8bit pwm pwm frequency 00: 01: 2 6 - 1 10: 2 7 - 1 11: 2 8 - 1 trun 8bit timer/ serial channel baud rate control reg. 0ffdbh brate1 brate0 prrun t4run t3run t2run t1run t0run r/w r/w 0000 0000 00 : 300/150 bps 01 : 1200/600 10 : 4800/2400 11 : 19200/9600 prescaler & timer run/stop control 0 : stop & clear 1 : run (count up) (4) timer/event counter control msb lsb symbol name address 7654 3210 82/86 toshiba corporation tmp90c802a/803a also refer to p3cr, trun register. note: br: baud rate generator (5) serial channel control msb lsb symbol name addres 7 6 5 4 3 2 1 0 scmod serial channel mode register 0ffe9h tb8 fixed at ? rxe wu sm1 sm0 sc1 sc0 r/w unde?ed 0 0 0 0 0 0 0 transmission bit-8 data in 9bit uart write ? 1 : receive enable 1 : wake up enable 00 : i/o interface 01 : uart 7bit 10 : uart 8bit 11 : uart 9bit 00 : to2trg 01 : br 10 : ? 11 : br 1/2 u a r t sccr serial channel control register 0ffeah rb8 oerr ferr r r (cleared to ??by reading) unde?ed 0 0 receiving bit-8 data 1 : error overrun 1 : error framing scbuf serial channel buffer register 0ffebh prohibit rmw rb7 tb7 rb6 tb6 rb5 tb5 rb4 tb4 rb3 tb3 rb2 tb2 rb1 tb1 rb0 tb0 r (receiving)/w (transmission) unde?ed (6) interrupt control msb lsb symbol name address 7654 3210 intel interrupt enable mask register 0ffe6h iet2 iet3 ie1 ierx ietx r/w 00? 0 0 1 : enable 0 : disable inteh (dmael) 0ffe7h 0 det0 det1 ie0 iet0 iet1 r/w r/w micro dma enable register 0?0 0 0 0 1 : enable 0 : disable 1 : enable 0 : disable dmaeh 0ffe8h derx detx r/w 0 0 1: enable 0 : disable irfl (p01cr) interrupt request flag & irf clear 0ffc2h prohibit rmw irf0 irft0 irft1 ext p1cr p0cr ? ww 000 0 0 0 interrupt request flag 1 : interrupt being requested p1, p2 controls 0 : i/o port 1 : address bus p1 controls 0 : in 1 : out p0 controls 0 : in 1 : out irfh 0ffc3h prohibit rmw irft2 irft3 irft4 irf1 irft5 irf2 irfrx irftx r (only irf clear code can be used to write) 00? 0 0 1 : interrupt being requested (irf is cleared to ??by writing irf clear code). toshiba corporation 83/86 tmp90c802a/803a symbol in ( ) denotes another name. 6. port section equivalent circuit diagram reading the circuit diagram basically, the gate singles written are the same as those used for the standard cmos logic ic [74hcxx] series. the dedicated signal is described below. stop: this signal becomes active ??when the hold mode setting register is set to the stop mode and the cpu executes the halt instruction. when the drive enable bit [drive] is set to ?? however, stp remains at ?? the input protection resistans ranges from several tens of ohms to several hundreds of ohms. po (d0 ~ d7) p1, p2 84/86 toshiba corporation tmp90c802a/803a p31, p37 p32, p35, p36 p33 p80, nmi toshiba corporation 85/86 tmp90c802a/803a p81 ?eset clk x1, x2 ?a 86/86 toshiba corporation tmp90c802a/803a |
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